基于层次化重复单元的FPGA结构描述方法  

Description Method for FPGA Architecture Based on Hierarchical Tile

作　　者：胡敏[1] 王健[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路国家重点实验室,上海201203

出　　处：《计算机工程》2013年第7期318-320,F0003,共4页Computer Engineering

基　　金：国家"863"计划基金资助项目(2012AA012001)

摘　　要：针对具有多种逻辑块和互连线结构的现代主流现场可编程门阵列(FPGA),给出一种通用的FPGA结构描述方法。根据FPGA硬件版图由几类重复单元在水平和垂直方向复制拼接而成的特点,提出基于层次化重复单元的FPGA结构模型,在该模型的基础上,通过定义一套完整的语法来描述FPGA。实验结果表明,该方法能正确描述FPGA硬件信息,并配合FPGA软件系统正常工作,具有结构通用和描述文件小的优点。Aiming at modem mainstream Field Programmable Gate Array（FPGA） with diverse logic blocks and interconnect lines, this paper proposes a universe FPGA architecture description method. Considering the fact that tiles are actually copied and pieced together to form the overall FPGA hardware layout, this paper proposes an FPGA architecture model based on hierarchical tile. According to the model, this paper also defines a set of complete and detailed syntactic rules to describe the FPGA architecture. Experimental results show that the description method can delineate FPGA hardware information, and work correctly with FPGA software system. It has common architecture and is small in size.

关 键 词：现场可编程门阵列 逻辑块 互连线 重复单元 结构模型 结构描述 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]