用于自对准Si MMIC的等平面深槽隔离工艺(英文)  

Quasi-Planarized Deep Trench Isolation Process for the Self-Aligned Si MMIC

作　　者：苏延芬[1] 梁东升[1] 胡顺欣[1] 邓建国[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《微纳电子技术》2013年第8期528-533,共6页Micronanoelectronic Technology

摘　　要：研究了在自对准硅MMIC中等平面深槽隔离工艺的实现。该工艺包括如下过程:首先应用各向异性刻蚀的Bosch工艺刻蚀出用于隔离埋集电极的1.6μm宽、9μm深的隔离槽,接着对隔离槽通过热氧化二氧化硅、淀积氮化硅和多晶硅的形式进行填充,然后再采用高密度等离子体刻蚀设备对多晶硅进行反刻,其刻蚀时间通过终点检测系统来控制,最后再刻蚀出0.8μm深的有源区硅台面和采用1.5～1.6μm厚的氧化层对场区进行填充,藉此来保证隔离槽和有源区处于同一个平面上。此深槽隔离工艺与目前的多层金金属化系统兼容,且该工艺不会造成明显的硅有源区台面缺陷,测试结果表明:在15 V下的集电极-集电极漏电流仅为10 nA,该值远低于全氧化填充隔离槽工艺的5μA。The quasi-planarized deep trench isolation process was realized for the self-aligned Si monolithic microwave integrated circuit （MMIC） fabrication. The trenches with geometry of 1.6 μm wide and 9 μm deep were achieved by the anisotropic etching with the Bosch process for isolating global buried collectors. Then the trenches were filled with thermal oxidation SiO2, LPCVD nitride and polysilicon. Subsequently the polysilicon was etched back with the end point detector （EPD） technology by high density plasma （HDP） etching system. In the end, a 0.8 μm deep Si active mesa was etched, and 1.5- 1.6μm thick field oxide was filled for the deep trench to be quasi-palanarized. Such a deep trench isolation process was proved to be acceptable for the subsequent multilayer gold-metallization process, and there were no obvious defects can be found on the Si active mesa. The test results show that the leakage current of the collector-to-collector is only 10 nA at 15 V, which is prior to all field-oxidation filling trench isolation process with the collector-to-collector leakage current of 5 μA.

关 键 词：深槽隔离 各向异性刻蚀 等平面 自对准 微波单片集成电路(MMIC) 

分 类 号：TN305.95[电子电信—物理电子学]