一种(50,32)BCH码高速并行编译码器设计  

High-speed parallel codec design for (50,32) BCH Codes

作　　者：崔媛媛[1] 张洵颖[1] 沈绪榜[1] 李伟[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《华中科技大学学报（自然科学版）》2013年第7期67-70,102,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：航天科技集团预研项目(2011AA120201)

摘　　要：针对太空环境的实际应用,为了满足32bit数据纠二检四,选用(50,32)BCH缩短码来实现.为了克服BCH编译码电路硬件结构复杂、计算周期长的缺点,对BCH码的编码和译码过程进行了研究,提出了一种求共有表达式的贪婪算法,使编码器与译码中求伴随式部分并行化设计后面积开销最小.通过使用直接译码算法求错误位置多项式,并去掉了复杂的除法操作,提高了译码器的效率.在SMIC 130nm的标准CMOS工艺下进行综合,结果表明:编码器的关键路径延迟约为1.10ns,而译码器只需4.91ns.The coding and decoding process were studied to improve BCH（bose-claudhuri-hocquenghem） codec hardware and reduce time-consuming.Aimed at space environment,（50,32） BCH shortened codes was selected to meet double error correcting four error detecting of the 32 bit data.A greedy algorithm for solving shared expressions was introduced.By using the proposed algorithm,the circuits of the BCH encoder and computing syndromes have minimum area.By using direct decoding algorithm to calculate the error location polynomial,and removing the complex division operation,the efficiency of the decoder was improved.Using SMIC（semiconductor manufacturing international corporation） 130 nm standard CMOS（complementary metal oxide semiconductor） process to synthesized,results show that the critical path delay of the encoder is 1.10 ns,and that of the decoder is only 4.91 ns.

关 键 词：译码器 纠错码 缩短码 BCH码 单粒子翻转 纠二检四 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]