高纵横选择比低损伤多晶硅栅的工艺实现  

Poly Gate Etching with High Aspect Ratio and Low Plasma Induced Defects

作　　者：苏延芬[1] 苏丽娟[1] 胡顺欣[1] 邓建国[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2013年第7期536-539,共4页Semiconductor Technology

摘　　要：分析了采用微波高密度等离子体刻蚀(HDP)系统刻蚀实现高纵横向刻蚀选择比、低等离子体损伤、精细线条尺寸的MOSFET多晶硅栅的可行性。研究了刻蚀用气体中CH4和SF6等离子体分别在多晶硅栅刻蚀当中的作用及其分别对刻蚀速率、多晶硅栅侧壁形貌的影响原理。提出了实现MOSFET多晶硅栅高速低损伤刻蚀及聚合物清洗相结合的两步刻蚀工艺技术。借助终点检测技术(EPD),通过优化各气体体积流量及合理选择两步刻蚀时间较好实现了较高的纵横向选择比、低刻蚀损伤及精细线条的MOSFET多晶硅栅刻蚀。The feasibility of high aspect ratio, low plasma induced defects poly silicon gate etching process with microwave high density plasma （HDP） was analyzed. The affects of the etching gas CH4 and SF6 on polysilicon gate etching and the influence principle on the etching rate and profile of the poly gate were studied. Then the two-step process combined with high aspect ratio low plasma induced defects polysilicon gate etching and polymer cleaning was presented. Recurring to the end point detect technology and through optimizing the gas flow rate and choosing rationally the process time, the high aspect ratio, low plasma induced defects and accurate line width controlling polysilicon gate etching process for the MOSFET were realized.

关 键 词：微波高密度等离子体(HDP) 纵横向刻蚀选择比 等离子体损伤 聚合物清洗 终点检测(EPD) 

分 类 号：TN405.98[电子电信—微电子学与固体电子学]