一种高速FPGA配置电路设计  

Design of a Fast FPGA Configuration Circuit

作　　者：毛劲松[1] 叶海江[1] 周灏[1] 王健[1] 来金梅[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2013年第4期479-485,共7页Journal of Fudan University：Natural Science

基　　金：国家"863"高技术研究发展计划(2012AA012001)资助项目

摘　　要：针对当前FPGA芯片编程下载(配置)电路结构上的不足导致位流下载回读吞吐率较低问题,设计了一种流水线编程下载电路结构,将位流下载分两级流水线并行实施,第一级通过快速解析位流的指令集实现数据包的分拆,第二级将解析出的数据包送达内部编程点相应的字线与位线.采用与电路结构兼容的32位并行CRC32技术校验下载位流,以增强位流下载可靠性,并采用帧ECC电路对回读位流进行单比特纠错与多比特检错(SECDED).验证结果表明,该设计在内部振荡器频率为150MHz的情况下外部配置端口的最高吞吐率为3 680Mbps,在内部振荡器频率为200MHz的情况下最高吞吐率为4 896Mbps.The current architecture of configuration circuit of FPGA limits the throughput of downloading the bitstream. A new architecture of FPGA configuration circuit, which contains a two-stage pipeline, is designed. The first pipeline stage splits the data package by parsing the hitstream instruction set, while the second stage transmits the data packages to the configuration word line and bit line. A 32 bits parallel CRC32 circuit compatible with the circuit structure is designed to verily the downloading bitstream. A ：Frame ECC circuit, which can correct one error bit and detect two or more error bits, is designed to verify the readback bitstream. The verification results show that the downloading throughput is up to 3 680 Mbps or 4 896 Mbps when the frequency of the internal oscillator is 150 MHz or 200 MHz, respectively.

关 键 词：现场可编程逻辑门阵列 编程下载 吞吐率 CRC32 ECC 

分 类 号：TN432[电子电信—微电子学与固体电子学]