PRESENT密码硬件语言实现及其优化研究  

Hardware Language Implementation and its Optimization of PRESENT

作　　者：李浪[1,2] 李仁发[2] 邹祎[1] 贺位位[1] 

机构地区：[1]衡阳师范学院计算机系,湖南衡阳421008 [2]湖南大学信息科学与工程学院,长沙410082

出　　处：《小型微型计算机系统》2013年第10期2272-2274,共3页Journal of Chinese Computer Systems

基　　金：国家自然科学基金项目(61173036)资助;湖南省教育厅青年项目(11B018)资助;湖南省博士后基金项目(897203005)资助;衡阳师范学院产学研基金项目(12CXYZ01)资助;湖南省十二五重点建设学科项目资助

摘　　要：PRESENT密码算法是2007年提出来的一种轻量级分组密码算法,适合于物联网环境下的安全加密.研究了PRESENT密码算法结构,在原算法结构基础上优化了密钥扩展的实现方法,把密钥扩展不在原算法图的右边实现,而是放入轮运算中.在硬件实现上,31轮重复运算只实现一次,采用31次调用完成,从而可以大幅节约PRESENT密码实现面积.最后,对PRESENT密码的各核心模块进行了Verilog HDL实现,并分模块进行了测试数据验证.经FPGA综合下载后,实验结果表明优化的PRESENT密码硬件语言实现正确,面积相对原始算法更少.PRESENT algorithm was designed in 2007. It is a lightweight block cipher algorithm. PRESENT is suitable for the security of encryption in the environment of the Internet of Things （IoT ）. First of all, the algorithm structure of PRESENT cipher is studied, The key expansion is optimized to realize based on the original algorithm. The key expansion is not implemented in the right edge of the chart but in round operation. Then, the 31 round of repetitive operation only implement once. Present main program recalls 31 times in the hardware implementation that can save more area. Finally, the core module of the PRESENT is realized with Verilog HDL which is tested for correction. The experimental results show that PRESENT is optimized properly with Verilog HDL. The area is less than original algorithm.

关 键 词：PRESENT 密钥扩展 优化 VERILOG HDL实现 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]