用于矩阵并行运算的加速板总线接口设计及其实验  

Design and Its Implementation of a Bus Interface Board Speeding Up the Parallel Matrix Operations

作　　者：孙杰[1] 唐怡亮[1] 翟宏琛[1] 张延忻[1] 

机构地区：[1]南开大学现代光学研究所,天津 300071

出　　处：《仪器仪表学报》2000年第6期632-635,共4页Chinese Journal of Scientific Instrument

基　　金：国家科委863计划 (863- 307-14-4(03));国家教委开放实验室资助项目

摘　　要：矩阵运算是计算机图像识别 ,特别是神经网络识别系统中频繁使用的基本运算之一。本文介绍了一种用电路硬件实现这种运算的微机总线接口板设计原理、编程方法和根据此技术实现的用于光电混合神经网络目标识别系统内矩阵相乘运算的微机 ISA总线接口实验。实验结果表明 ,应用这种新方法实现的运算不仅速度快 ,而且程序简单 ,能一次完成 4K字节× 4K字节数据量的矩阵相乘运算。Matrix operation is one of the basic operations frequently used in the computer system, especially in the neural network system for pattern recognition. In this paper, the designing principle and related programming principle as well as a PC bus interface board of this operation in a hybrid neural network system for pattern recognition implemented with interface circuits are introduced. The experiment results show that, by employing this new kind of implementation, not only has the operation been speeded up, but also has the programs been simplified. As a result, matrix multiplication with 4K×4K bytes can be easily executed in a single operation. The principles of the design and the related skills will be generally applicable in all the systems where matrix operations are frequently needed.

关 键 词：矩阵运算 总线 存储器 神经网络 计算机 

分 类 号：TP336[自动化与计算机技术—计算机系统结构] TP301.6[自动化与计算机技术—计算机科学与技术]