一款32位定点DSP电路的设计  

A Design of 32-Bit Fixed-Point DSP Circuit

作　　者：薛海卫[1] 张庆文[1] 王月玲[1] 徐新宇[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2013年第9期22-25,30,共5页Electronics & Packaging

摘　　要：文章通过对32位定点DSP的体系结构及其设计方法的研究,重点阐述了32位定点DSP中CPU包括ALU、MPY、ARAU、流水线、指令系统和总线接口等关键逻辑部件工作原理,对各个逻辑部件的设计思路和实现方法进行了分析描述。采用基于标准单元正向设计方法,设计了一款32位指令集的定点DSP电路,该电路采用哈佛总线结构,可以在单周期内实现16×16位有符号整数乘法、32位累加和32位数据的算术逻辑运算,处理精度高。该电路采用0.5μm 1P3M CMOS工艺流片,集成度7万门,工作频率可达36 MHz,动态功耗594 mW。By researching the structure of 32-bit DSP and its design method, the theory of critical parts in 32-bit DSP, such as ALU MPY ARAU pipeline and instruction set, is demonstrated in this paper. The design and implementation of the logic blocks are analyzed. A 32-bit fixed-point DSP circuit is designed by using standard cell design methodology. The circuit is based on the HARVARD bus structure and can implement 16~16-bit signed integer multiply, 32-bit ACC and 32-bit logic arithmetic. The DSP circuit is fabricated in 0.5 ~tm IP3M CMOS process. Its integrity is 70 K gates. The operation frequency is 36 MHz and power consumption is 594 mW.

关 键 词：32位 定点DSP 体系结构 CPU 

分 类 号：TN402[电子电信—微电子学与固体电子学]