体硅集成电路版图抗辐射加固设计技术研究  

Research on Design of Radiation Hardened Layout for Integrated Circuit in Si Technology

作　　者：田海燕[1] 胡永强[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2013年第9期26-30,共5页Electronics & Packaging

摘　　要：辐射效应是电路在太空等领域应用时遇到的首要问题,常常会引起电路出错或失效。为了满足抗辐射电路设计的需求,必须提高电路抗辐射效应的能力。文章分析了辐射效应对器件产生的影响。针对电路在辐射环境中应用时存在的问题,文章从版图抗辐射设计加固的角度出发,介绍了抗总剂量的环形栅、倒比例器件,以及抗单粒子昆倾效应抗辐射版图的设计方法。在电路设计时,通过上述几种版图设计方法的应用,可以提高电路的抗辐射性能,进而提高电路的可靠性。Radiation effect is the first problems we must face when circuit is used in space, it will arise the mistakes and invalidation of integrated circuit. In this paper, we analyze the effect of radiation for device, firstly. And for improving the questions when circuit used in space, we introduce the design measure of annular-gate, inversion-gate and defend Quenching effect from point of layout design for radiation hardened. When we design the integrated circuit which used in space, we could use these design measures which are talked in this paper. It could improve the circuit performance of radiate.

关 键 词：辐射效应 版图设计 可靠性 

分 类 号：TN402[电子电信—微电子学与固体电子学]