高压LDMOS准饱和效应研究  

Research on the Quasi-saturation Effect of High-voltage LDMOS

作　　者：翟宪振[1] 吴海峰[1] 罗向东[1] 

机构地区：[1]江苏省专用集成电路设计重点实验室南通大学,江苏南通226019

出　　处：《固体电子学研究与进展》2013年第5期466-471,共6页Research & Progress of SSE

基　　金：江苏省自然科学基金资助项目(BK2012656)

摘　　要：借助于SILVACO TCAD仿真工具,研究了高压LDMOS电流准饱和效应(Quasi-saturation effect)的形成原因。通过分析不同栅极电压下漂移区的耗尽情况以及沟道与漂移区电势、电场和载流子漂移速度的分布变化,认为当栅压较低时,LDMOS的本征MOSFET工作在饱和区,栅压对源漏电流的钳制明显,此时沟道载流子速度饱和;而在大栅压下,随着沟道导电能力的增加以及漂移区两端承载的电压的增大,本征MOSFET两端压降迅速降低,器件不能稳定地工作在饱和区而进入线性工作区,此时沟道中的载流子速度不饱和。LDMOS器件的源漏电流的增大主要受漂移区影响,栅压逐渐失去对器件电流的控制,此时增大栅压LDMOS器件的源漏电流变化很少,形成源漏电流的准饱和效应。最后,从器件工作过程对电流与栅压的关系进行了理论分析,并从理论结果对电流准饱和效应进行了深入分析。The quasi-saturation effect in LDMOS devices with high breakdown voltage was investigated with SILVACO TCAD tools. Under different gate voltages, the potentials,electric fields and electron drifting velocities in both channel and drift region were analyzed in detailed. When the gate voltage was low, the intrinsic MOSFET of the LDMOS was operated at saturation region, its drain current was mainly controlled by the gate voltage. When the gate voltage in- creased, the ＇S-D＇ voltage of the intrinsic MOSFET in LDMOS was lower than the saturated op- eration voltage. Then the intrinsic MOSFET in LDMOS would work in linear region. The S-D current of LDMOS device was mainly controlled by drift region. And its S-D saturated current was increased very slow, far lower than the increase of the gate voltage. Then, the quasi-satura- tion effect occurred in LDMOS. Finally, numerical theoretical analyses were applied to explain the quasi-saturation effect in LDMOS in depth.

关 键 词：横向双扩散金属氧化物半导体晶体管 准饱和效应 线性工作区 

分 类 号：TN386[电子电信—物理电子学]