基于Avalon总线的图像处理IP核的设计  

Design of image processing IP core based on Avalon bus

作　　者：蔡国洋[1] 赵毅[1] 余良辉[1] 

机构地区：[1]国电南瑞科技股份有限公司,江苏南京210061

出　　处：《现代电子技术》2013年第24期86-89,共4页Modern Electronics Technique

摘　　要：IP核是SoPC系统的重要组成部分,针对如何高速、有效地实时处理图像的问题,提出了一种基于Avalon总线的图像处理IP核的设计方法。根据最新的数字视频国际编码标准和颜色空间理论,用Verilog HDL硬件描述语言完成IP核的功能实现,IP核被设计为Avalon总线从端口,通过Avalon总线与NiosⅡ处理器进行通信。IP核通过SignalTapⅡ在线验证,可修改其参数使之满足不同系统的需求。该方法具有良好的通用性,提高了系统的兼容性,能帮助其他用户明显缩短实时图像处理系统项目的研发周期、降低工作强度。IP core is an important part of SoPC system. A method of designing the image processing IP core based on Ava- lon bus is proposed for fast and effective real-time image processing. The function of IP core is realized by Verilog HDL according to the latest international coding standard of digital video and the theory of color space. IP core is designed as Avalon slave port, which communicates with Nios II through Avalon bus. IP core can meet the needs of different systems through online verification of SignalTap II to modify IP core＇s parameters. The method has strong universality, can improve the compatibility of the system and help other users to significantly cut down the development period and reduce the work intensity.

关 键 词：SOPC IP核 图像处理 VERILOG HDL AVALON总线 SignalTap II 

分 类 号：TN964-34[电子电信—信号与信息处理]