中间电平对CMOS数字电路的影响  

Effects of CMOS Digital IC on Middle Level

作　　者：李兴鸿[1] 赵俊萍[1] 赵春荣[1] 林建京[1] 梁云[1] 

机构地区：[1]北京时代民芯科技有限公司,北京100076

出　　处：《电子产品可靠性与环境试验》2013年第6期13-16,共4页Electronic Product Reliability and Environmental Testing

摘　　要：很多情况都可以导致CMOS数字集成电路产生大的电源电流,但以CMOS的输入处于Vilmax与Vihmin之间的转折区而产生的大电流最为常见;而且其影响很重要,甚至会导致闩锁效应而对电路造成损坏。转折区的危险电平由管脚浮空、误操作、输入脉冲的上下沿和双向I/O这几种状态所产生。对每一种状态的影响及其原因进行了详细的分析,给出了解决的方法。对电路设计、试验、测试和分析具有一定的参考价值。Many cases can lead to higher current of the power supply in digital CMOS ICs. It is common that the input region of CMOS between Vilmax and Vihmin （transition width） can produce higher current. This is very important because it can lead to latch-up and destroy ICs. The dangerous transition width is produced by floating pins, misoperation, the rising and falling edge of input pulse and hi-directional I/O. The effects of every state and their causes are analyzed, and the solutions are given, which may be a good reference to design, experiment, test and failure analysis of ICs.

关 键 词：互补金属氧化物半导体 数字集成电路 中间电平 大电流 影响 

分 类 号：TN432[电子电信—微电子学与固体电子学]