用于时钟恢复电路的低抖动可变延迟线锁相环电路  

A Phase Locked Loop for Clock Recovery Circuit Using Low-Jitter Variable Delay Line

作　　者：李曙光[1] 朱正[1] 郭宇华 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《微电子学》2001年第1期49-52,57,共5页Microelectronics

摘　　要：文中给出了一个基于压控可变延迟线的电荷泵锁相环电路的设计 ,用于时钟恢复电路中采样时钟沿的定位 ,它的工作不受环境和工艺的影响 ,保证了采集数据的准确性。应用于延迟线中的改进的延迟单元有效地减小了相位抖动 ,环路滤波电路的设计避免了电荷重新分配引入的影响。电路采用 0 .35μm TSMC的 MOS工艺 ,在 3.3V的低电压下工作 ,模拟得到在最坏情况下 ,单个延迟模块的相位抖动为 2 0 ps,输出静态相位误差仅A charge pump phase-locked loop(PLL) based on voltage-controlled delay line (VCDL) is presented, which is used to locate the sampling clock edge in the clock recovery circuit. This design is independent on environment and process. The improved delay unit in VCDL efficiently lowers the output jitter and a low-pass filter (LPF) is designed to avoid the charge-sharing error. Using 0 35 μm TSMC process, the circuit can operates at a low voltage of 3 3 V.In the worst-case condition, simulated jitter of single delay module is 20 ps and static phase error is only 45 ps between input and output.

关 键 词：锁相环 时钟恢复电路 延迟线 锁相环电路 

分 类 号：TN812[电子电信—信息与通信工程]