两级非平衡超结SOILDMOS高压器件  

High Voltage SOI LDMOS with Two-Stage Unbalanced Super Junction

作　　者：王文廉[1] 

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《微电子学》2014年第1期97-100,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61106077);山西省青年基金资助项目(2010021015-3)

摘　　要：针对SOI功率集成电路,提出一种具有两级非平衡超结的SOI LDMOS高压器件。新结构通过调节超结的掺杂浓度,在漂移区形成两级超结结构。在器件反向耐压时,源端的超结n区被快速耗尽,过剩的p型电荷可以降低源端的峰值电场,同时提高漂移区中部的电场;而漏端的超结p区被快速耗尽,过剩的n区与n型外延层共同提供补偿电荷,这种阶梯分布的电荷补偿进一步优化了横向电场分布。这种两级非平衡超结结构缓解了横向超结器件中的衬底辅助耗尽效应,可提高器件的耐压。三维器件仿真结果表明,在漂移区长度为15μm时,该器件的耐压达到300V,较常规的超结器件和具有缓冲层的超结器件分别提高122%和23%。A new high voltage SOI LDMOS with two-stage unbalanced super junction （SJ） was proposed for SOI power integrated circuits （PICs）. In drift region of the new structure, a two-stage unbalanced SJ was implemented by adjusting doping concentration of SJ. On off-state, n-pillars of SJ in source region were quickly depleted, resulting in excessive p-type charges, which reduced electric field peak in source region and increased electric field in the middle of drift region. On the other hand, p-pillars of SJ in drain region were quickly depleted, leading to excessive n-type region, which, together with n-type epi-layer, provided compensation charges. The step doping of compensation charges further optimized electric field distribution. Two-stage unbalanced SJ structure relieved substrate-assisted depletion effects in lateral SJ devices, which improved breakdown voltage of the device. Numerical simulation results indicated that the proposed structure with a drift length of 15μm achieved a breakdown voltage of 300 V, a 122% and 23% increase, compared with conventional SJ device and buffered SJ device, respectively.

关 键 词：超结 LDMOS SOI 功率集成电路 

分 类 号：TN386[电子电信—物理电子学]