54位高速冗余二进制乘法器的设计  

High-Speed 54×54-b Redundant Binary Multiplier Design

作　　者：崔晓平[1] 高鹏辉[1] 尹洁珺 丁晶[1] 李启[1] 

机构地区：[1]南京航空航天大学电子信息工程学院,江苏南京210016

出　　处：《微电子学与计算机》2014年第4期140-143,共4页Microelectronics & Computer

摘　　要：冗余二进制(RB)数是一种有符号数的表示方法,利用冗余二进制算法的进位无关特性和规整的结构,可以设计高速RB并行乘法器.系统地研究了RB乘法器的算法和结构,给出了基于修正Booth算法,RB部分积压缩树和RB-NB转换器的54b乘法器的设计过程,并利用并行前缀/进位选择混合加法器对RB-NB转换器进行优化设计.采用Verilog HDL对乘法器进行描述,并在ModelSim平台上进行仿真验证,在SMIC 0.18mm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行综合,得到54bRB乘法器的延时可达到3.97ns,面积是409 293mm2.Redundant binary representation is one of the signed-digit number systems. High modularity and the carry-free feature of RB arithmetic can be used to design high-speed parallel multipliers. In this paper, the algorithm and structure of RB multiplier is systematically studied. The 54-bit RB multiplier is designed by the modified Booth algorithm, RB partial product accumulator and RB-NB converter. The hybrid parallel-prefix/carry- select adder is used to design optimized RB-NB converter. The multiplier has been realized by Verilog HDL and simulated in the ModelSim platform. Under SMIC 0. 18 mm standard process library, the synthesis results of this design by Design Compiler show that the delay can be reduced to 3. 97 ns and the area is 409 293 mm2.

关 键 词：冗余二进制乘法器 布斯编码 部分积 并行前缀加法器 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]