考虑缺陷率模型的多项目晶圆布图规划算法  

Multi-project Wafer Floorplanning Algorithm Considering Defect Rate Model

作　　者：张腾[1] 史峥[1] 廖海涛[1] 

机构地区：[1]浙江大学电气工程学院超大规模集成电路设计研究所,杭州310027

出　　处：《计算机工程》2014年第4期258-261,268,共5页Computer Engineering

基　　金：国家自然科学基金资助项目(61204111)

摘　　要：针对随机缺陷会降低多项目晶圆实际产出的问题,提出一种新的多项目晶圆布图规划算法。通过在布图规划中引入缺陷率模型的方法,增加芯片产量的裕量,降低因随机缺陷造成的产量损失。同时优化模拟退火流程,使得在布图尺寸约束条件下,布图规划过程能够跳出局部最优解陷阱。对工业实例进行布图规划的结果表明,该算法能够接受不满足布图尺寸约束条件的中间结果,从而遍历解空间,得到全局最优的布图,并且相对已有算法,使用相同数量晶圆进行切割时,算法的布图结果增加了137%的芯片产量的总裕量,同时,降低了25%的工作芯片所需要生产的晶圆数量。To address yield loss from random defects, a new Multi-project Wafer（MPW） floorplanning algorithm is proposed. This proposed algorithm can increase production margin as well as reduce fabrication loss caused by random defects by introducing defect models, and simulated annealing process is modified to escape locally optimal solution traps under Reticle Size Constraint（RSC）. By carrying out industrial cases, the proposed algorithm can search solution space and find global optimal solution by accepting interim floorplanning results, and floorplanning result illustrates proposed algorithm increases total chip production margin by 137%, and reduces required wafer number to obtain enough volume of chip for each intezrated circuit design by 25%. compared with existin~ algorithms.

关 键 词：多项目晶圆 布图规划 模拟退火算法 代价函数 缺陷率模型 布图尺寸约束 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]