一种用于产生多相时钟的延时锁定环  

A Delay-Locked Loop for Multiphase Clock Generation

作　　者：马昭鑫 黄鲁[2] 方毅[2] 

机构地区：[1]中国科学技术大学电子科学与技术系,合肥230027 [2]中国科学技术大学信息科学实验中心,合肥230027

出　　处：《微电子学》2014年第2期153-156,162,共5页Microelectronics

基　　金：国家科技重大专项资助项目(2011ZX03004-002-01)

摘　　要：分析并实现了一种用于产生多相时钟的延时锁定环电路。利用重复延时线和周期检测器,避免了复位信号和错误锁定的问题;采用信号路径对称的鉴相器,减小了抖动;使用电流舵技术,提高了电荷泵的开关速度。基于SMIC 0.18μm CMOS工艺,实现了一种产生32相时钟的延时锁定环,芯片核心尺寸为0.7mm×0.55mm,参考时钟频率范围为20~150MHz。仿真结果显示,在输入参考时钟频率为60MHz时,最长锁定时间为1.9μs,抖动为1ps,1.8V电源电压下的功耗为31.5mW。A delay-locked loop（DLL）to generate multiphase clock was implemented.In this circuit,a duplicate voltage controlled delay line and a cycle period detector were employed to avoid reset signal and＂false locking＂;a phase detector with symmetrical path was adopted to reduce jitter;and a current steering technology was used to improve switching speed of charge pump.The proposed DLL,which was capable of generating 32-phase clocks, was implemented in SMIC 0.18μm CMOS process,and it occupied a chip area of 0.7mm×0.55mm.Simulation results indicated that the DLL had a reference frequency range from 20MHz to 150MHz,and a maximum locking time of about 1.9μs and 1-ps jitter was achieved at 60MHz input reference frequency.The circuit dissipates 31.5 mW of power from 1.8Vsupply.

关 键 词：延时锁定环 多相时钟 压控延时单元 电荷泵 抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学]