数字音频广播基带解码芯片的可测试性设计  

Design-for-Testability of Baseband Decoder IC for Digital Audio Broadcasting

作　　者：张红升[1] 王国裕[1] 陆明莹[1] 

机构地区：[1]重庆邮电大学微电子工程重点实验室,重庆400065

出　　处：《微电子学》2014年第2期269-272,共4页Microelectronics

基　　金：重庆市科委基础与前沿研究计划项目(cstc2013jcyjA40006);重庆市教委科学技术研究项目(KJ130530);重庆邮电大学科研基金资助项目(A201211)

摘　　要：介绍了一款数字音频广播基带解码芯片的可测试性设计,主要包括扫描测试(Scan Test)、存储器内建自测试(BIST)和电流测试。为了提高测试可靠性和芯片良品率,在扫描测试中,采用分级时钟树综合方法;在存储器测试中,采用分等级、分区域的RAM测试策略。为了降低设计复杂度,将所有测试结果都直接与芯片IO复用,并采用封装后再测试的方法,以降低测试成本。最终使用12条扫描链,扫描测试的覆盖率为96.2%。芯片量产后的测试结果表明,经过检测后的芯片在产品应用中全部工作正常,证明了可测试性设计的有效性。Design-for-testability of a baseband decoder chip for digital audio broadcasting was presented,in which scan test,built-in self test（BIST）and current test were included.In order to improve test reliability and chip yield, a hierarchical clock tree synthesis method was applied in scan test circuit,and a classification and partition method was used for RAM BIST.All test signals were multiplexed with IOs of the chip,to reduce complexity of the design. All tests were performed after the chip was packaged,so as to cut down test cost.The circuit had a scan-test coverage of 96.2% with 12scan-chains.It has been shown that all tested chips from mass production operated properly,which proved the efficiency and reliability of the proposed design for testability.

关 键 词：基带解码芯片 可测试性设计 扫描测试 内建自测试 

分 类 号：TN47[电子电信—微电子学与固体电子学]