Verilog HDL语言的AES密码算法FPGA优化实现  

FPGA optimal implementation of AES based on Verilog HDL

作　　者：李浪[1,2] 邹祎[1] 李仁发[2] 李肯立[2] 

机构地区：[1]衡阳师范学院计算机科学系,湖南衡阳421002 [2]湖南大学信息科学与工程学院,长沙410082

出　　处：《重庆大学学报（自然科学版）》2014年第6期56-64,共9页Journal of Chongqing University

基　　金：国家自然科学基金资助项目(61133005);湖南省教育厅青年资助项目(11B018);湖南省博士后基金资助项目(897203005);衡阳师范学院产学研基金项目(12CXYZ01)

摘　　要：AES密码算法是目前广泛使用的一种加密算法。为了对AES算法进行优化,通过对密钥扩展模块重复调用,实现代码的高效利用。具体方法为在AES算法进行加解密运算时,其中所需的密钥可在其他模块执行时重复调用,即一次生成十轮密钥,通过控制模块实现轮密钥加运算。详细叙述了改进后AES算法的Verilog HDL硬件语言实现,特别是对具体实现过程中关键核心代码进行了清晰描述,经modelsim6.1f仿真验证正确后进行了FPGA硬件实现,对FPGA硬件实现进行了实验结果正确性验证。实验结果表明,优化后的AES算法在Xilinx Virtex-V FPGA上仅占用了3 531个Slice,5 522个LUT,与同类加密算法实现所需的资源数对比,在性能同等条件下占用面积更少,可满足芯片的较小面积应用需求,从而可以使得AES算法应用于目前流行的各种小面积智能卡上。AES algorithm is a widely used cryptographic algorithm. To improve AES algorithm, it＇s proposed to repeatedly call key expansion module to realize efficient use of the code. Ten-round keys are generated at the same time, and operations of add round key are achieved by the control module. The key is called repeatedly when the AES algorithm is running for eneryption and deeryption. The realization of AES is verified by modelsim6, lf. AES algorithm is designed with Verilog HDL,and a clear description about the critical core code realization of the process is proposed. The hardware implementation is verified by FPGA. Experimental results show that the optimized AES algorithm has only 3 531 slices,5 522 LUTs on a Xilinx Virtex-V FPGA. Our implementation occupies less area and it can get the same performance with comparing with other implementations of the AES, so it can meet application requirements of smaller chip, which canmake the AES algorithm be applied to the popular small area on the smart card. It can make the AES algorithm use in the smart card.

关 键 词：AES算法 VERILOG HDL FPGA实现 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]