双层金属布线硅栅CMOS门阵列电路制造工艺技术研究  

High Performance Double Level Metal CMOS Gate Array Technology

作　　者：郑养鉥 张敏[1] 凌栋忠[1] 吴璘 顾惠芬[1] 郑庆云[1] 邱斌 

机构地区：[1]中国科学院上海冶金研究所,上海200233

出　　处：《Journal of Semiconductors》1993年第1期36-42,共7页半导体学报（英文版）

摘　　要：采用双层金属布线可以提高集成电路的集成密度、集成度和速度。本文报道了双层金属布线工艺技术成功地应用于制造标准3μm硅栅CMOS 500门、1200门、2000门多种门阵列专用大规模集成电路。本文对双层金属布线硅栅CMOS门阵列电路制造工艺技术的几个关键技术问题进行讨论。Multilevel metallization in VLSI interconnect is an important technology in IC fabrication process. It is a dominant factor in determining the density, device speed, yield and reliabilityof ICs. Several key technologies in double level metal Si-gate CMOS have been discussed.More than ten chips of double level metal 3μm Si-gate CMOS gate arrays have been sucessfullymanufactured by using the technology. The purpose of this paper is to present a newly developedCMOS technology for ASIC and to demonstrate high speed performance of the realizedCMOS devices. The device technologies, metallization technique,contact resistance andmetal step coverage are described.

关 键 词：集成电路 多层布线 CMOS 工艺 电路 

分 类 号：TN470.597[电子电信—微电子学与固体电子学]