一种新的CMOS组合电路最大功耗快速模拟方法  

A Novel Approach to Fast Simulate Maximum Power Dissipation of CMOS Combinational Circuits

作　　者：骆祖莹[1] 闵应骅[2] 杨士元[1] 

机构地区：[1]清华大学自动化系,北京100084 [2]中国科学院计算技术研究所网络研究室,北京100080

出　　处：《计算机辅助设计与图形学学报》2001年第7期577-581,共5页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金重点项目 (6 97330 10 )资助

摘　　要：过大的峰值功耗会使芯片承受过大的瞬间电流冲击 ,降低芯片的可靠性及性能 ,因此有效地对电路最大功耗做出精确的估计非常重要 .由于在实际电路中存在时间延迟 ,而考虑延时的电路功耗模型计算量较大 ,因此用模拟方法求取电路最大功耗非常耗时 .为了在尽可能短的时间内对 VL SI电路的最大功耗做出较为可信的估计 ,首次提出了二阶段模拟加速方法 .对 ISCAS85电路集的实验结果表明 。High peak power makes VLSI circuits suffer from great instantaneous current and severe electro migration, which may lower chip's reliability and performance. Thus it is very imperative to estimate effectively accurate peak power dissipation of circuits. Because it has to take long time to compute power dissipation of CMOS circuits with delay, it needs extensive CPU time to simulate the maximum power consumption of circuits. In order to get an efficient estimation of the peak dissipation of CMOS combinational circuits in a tolerable period, this paper proposes a novel hierarchical approach. Experiments with the ISCAS85 benchmark circuits demonstrate that this approach saves much more time and can give an accurate estimation of peak power dissipation.

关 键 词：最大功耗估计 CMOS组合电路 超大规模集成电路 芯片集成度 

分 类 号：TN47[电子电信—微电子学与固体电子学]