Novel Substrate pn Junction Isolation for RF Integrated Inductors on Silicon  

新颖的衬底pn结隔离型硅射频集成电感(英文)

作　　者：刘畅[1] 陈学良[1] 严金龙[1] 

机构地区：[1]中国科学院上海冶金研究所微电子学分部,上海200233

出　　处：《Journal of Semiconductors》2001年第12期1486-1489,共4页半导体学报（英文版）

摘　　要：A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the Si substrate. The substrate pn junction can be realized by using the standard silicon technologies without any additional processing steps.Integrated inductors on silicon are designed and fabricated. S parameters of the inductor based equivalent circuit are investigated and the inductor parameters are calculated.The impacts of the substrate pn junction isolation on the inductor quality factor are studied.The experimental results show that substrate pn junction isolation in certain depth has achieved a significant improvement.At 3GHz,the substrate pn junction isolation increases the inductor quality factor by 40%.提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .

关 键 词：Si integrated inductor quality factor eddy current pn junction isolation 

分 类 号：TM55[电气工程—电器]