高速全耗尽CMOS/SOI 2000门门海阵列  

A High Speed Fully Depleted CMOS/SOI 2000 Gate Sea-Of-Array

作　　者：刘新宇[1] 孙海峰[1] 海朝和 刘忠立[2] 吴德馨[1] 

机构地区：[1]中国科学院微电子中心,北京100029 [2]中国科学院半导体所,北京100029

出　　处：《电子学报》2001年第8期1129-1131,共3页Acta Electronica Sinica

摘　　要：本文对全耗尽CMOS/SOI 2 0 0 0门门海进行了研究 ,阵列采用宏单元结构 ,每个宏单元包括 2× 8个基本单元和 8条布线通道 ,其尺寸为 :92 μm× 86 μm .2 0 0 0门门海阵列采用 0 8μm全耗尽工艺 ,实现了 10 1级环形振荡器和 4～ 12 8级分频器电路 ,在工作电压为 5V时 ,0 8μm全耗尽CMOS/SOI 10 1级环振的单级延迟为Fully-depleted CMOS/SOI 2000 gate sea-of-array are described in the paper.The structure of macrocell is used,Including 2~{!A~}8 basic cells and eight channels,wi th size is 92~{&L~}m~{!A~}86~{&L~}m.The SOG(Sea-Of-Array) were developed with 0.8~{&L~}m Fully -depleted CMOS/SOI technology.Some frequency dividers and ring oscillators are built on it.Unloaded 101 stage 0~{*1~}8~{&L~}m fully-depleted ring oscillators reported here have very good speed performance.Under 5V supply voltage,the delay per sta ge reaches 45ps.

关 键 词：门海阵列 薄膜全耗尽SOI CMOS SOI 集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]