CPLD/FPGA的优化设计  

Optimization design in CPLD/FPGA

作　　者：熊国海[1] 关德群 万钧力[1] 

机构地区：[1]三峡大学电气信息学院,湖北宜昌443002 [2]哈尔滨克罗拉太阳能电力公司,哈尔滨150046

出　　处：《电测与仪表》2002年第2期42-44,共3页Electrical Measurement & Instrumentation

摘　　要：CPLD/FPGA面向速度或面向面积进行优化设计,在大多数情况下这两种选择是矛盾的。对速度进行优化设计,需要较多资源;对面积进行优化往往会导致系统速度降低。本文提出采用流水线设计、资源共享和预进位处理的方法解决了这个问题。In the most cases,optimization design in CPLD/FPGA in speed and area are incompatible.More resource is needed in optimization design in speed;system speed usu-ally is reduced in optimization design in area.The problem can be solved by the offered method in this paper,which pipelining design,resource sharing and carry beforehand process are used.It is served as the technicians.

关 键 词：速度 面积 优化设计 CPLD/FPGA 高密度可编程逻辑器件 

分 类 号：TN791[电子电信—电路与系统]