一种新型的晶体管级改进Booth编码单元电路  

A New Transistor-Level Circuit for Modified Booth's Encoder

作　　者：卢君明[1] 林争辉[1] 

机构地区：[1]上海交通大学大规模集成电路研究所,上海200030

出　　处：《微电子学》2002年第3期212-214,218,共4页Microelectronics

基　　金：美国国家科学基金 (NSF)资助项目 (5 978East Asia and Pacific Program- 96 0 2 4 85 )

摘　　要：文章提出了一种新的高速低功耗晶体管级改进 Booth编码单元电路。该电路组合了CMOS逻辑电路和传递管逻辑电路 ,采用高速低功耗 XOR和 XNOR电路 ,仅用了 30个晶体管就实现了改进 Booth编码。在 0 .35 μm的工艺条件下 ,HSPICE的仿真结果表明 ,电源电压 3.3V和频率 1 0 0 MHz条件下 ,该改进 Booth编码电路的延迟为 0 .34ns,平均功耗为 0 .1 3m W。Design of a new high speed, low power and area efficient circuit for Modified Booth's Encoder is presented in the paper This circuit combines the CMOS logic circuits and pass transistor (PT) logic circuits By utilizing the new high speed low power XOR and XNOR circuits, only 30 transistors are used to implement the Modified Booth's Algorithm Experimental results showed that the worst case delay of the new circuit, which is based on a 0 35μm CMOS process, is 0 34 ns at a supply voltage of 3 3 V, and the average power dissipation is 0 13 mW at 100 MHz

关 键 词：晶体管 单元电路 BOOTH编码 逻辑电路 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]