基于Cavity基板技术的堆叠芯片封装设计与实现  

A Package Design and Realization for Die-stacking System Based on Cavity-substrate Technology

作　　者：谢慧琴[1] 曹立强[1,2] 李君[1,2] 张童龙 虞国良 李晨 万里兮[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]华进半导体封装先导技术研发中心有限公司,无锡214135 [3]南通富士通微电子股份有限公司,南通226006

出　　处：《科学技术与工程》2014年第20期224-228,共5页Science Technology and Engineering

基　　金：国家重大科技专项(2011ZX02601-002-02)资助

摘　　要：介绍了一种适用于堆叠芯片的封装结构。采用层压、机械铣刀开槽等工艺获得Cavity基板,通过引线键合(wire bonding,WB)和倒装焊(flip chip,FC)两种方式实现堆叠芯片与基板的互连,并将堆叠芯片埋入Cavity基板。最后,将包含4款有源芯片和22个无源器件的小系统高密度集成在一个16 mm×16 mm的标准球栅阵列封装(ball grid array,BGA)封装体内。相比较于传统的二维封装结构,该封装结构将封装面积减小了40%,封装高度减小500μm左右,并将堆叠芯片与基板的互连空间增加了2倍。对这款封装结构的设计过程进行了详细的阐述,并验证了该封装设计的工艺可行性。A package design for die-stacking system was presented.The cavity-substrate was fabricated by lamination and mechanically milling technology.Hybrid interconnection including both wire bonding （WB） and flip chip （FC） was used.The stacked dies were embedded into the cavity substrate.Finally,four chips and twenty-two passives were packed in a 16 mm × 16 mm standard ball grid array （BGA） package.In contrast with earlier 2D package design version,the packaging area was reduced by 40％ and the package height was decreased by about 500 μm.In addition,the fan-out area for the stacked die was tripled.The design progress and how the design was realized were delicately elaborated.

关 键 词：Cavity基板 堆叠芯片 小型化 高密度 

分 类 号：TN41[电子电信—微电子学与固体电子学]