偏置电压交变的时分反馈闭环加速度计(英文)  

Improved Structure of Time-Divided Closed-Loop Accelerometer by Alternating the Voltage Biasing

作　　者：黄靖清[1] 赵猛[1] 张婷婷[1] 陈中建[1] 伍峰[1] 洪理琛[1] 刘大河[1] 张雅聪[1] 鲁文高[1] 高成臣[1] 郝一龙[1] 

机构地区：[1]北京大学微纳电子学系微纳米/纳米加工技术国家级重点实验室,北京100871

出　　处：《北京大学学报（自然科学版）》2014年第4期729-733,共5页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：863计划(2008AA042201)资助

摘　　要：提出一种改进结构的时分反馈闭环加速度计,该结构使用负系数的PID控制器,只需要一个运算放大器。改进后的结构减小了读出电路的芯片面积,同时省去一个运算放大器和两个大电阻,因此能降低系统噪声。读出电路采用0.35μm高压CMOS工艺,并包含自检测功能。测试结果显示,在自检测模式下,闭环加速度计的线性度为99.72%。在DC到200 Hz内,输出噪声电压均方根值约为140μV。A new structure of time-divided closed-loop accelerometer is proposed. It requires only one operational amplifier as a negative-coefficient PID is just sufficient. This structure not only reduces the area consumption of the whole chip of the readout circuit, but also lowers the equivalent input noise acceleration as one operational amplifier and two large resistors are reduced. The readout circuit is fabricated using 0.35 μm HV CMOS process, with self-test function included. Test results show that the linearity of 99.72% is achieved under self-test mode. The root-mean-square output noise voltage is around 140 μV from DC to 200 Hz.

关 键 词：比例积分微分控制器 闭环 加速度计 自检测 微机电系统 

分 类 号：TN432[电子电信—微电子学与固体电子学]