基于PCIE2.0的物理层弹性缓冲器设计  

Design of Elastic Buffer at Physical Layer Based on PCIE2.0

作　　者：郑乾[1,2] 晏敏[1] 赵建中[2] 李优[2] 张锋[2] 

机构地区：[1]湖南大学物理与微电子科学学院,长沙410082 [2]中国科学院微电子研究所专用集成电路与系统研究室,北京100020

出　　处：《计算机工程》2014年第10期71-75,共5页Computer Engineering

基　　金：国家"863"计划基金资助项目(2011AA010403)

摘　　要：弹性缓冲器是PCIE,USB等高速串行总线物理层接收器的重要组成部分,用于物理层接收器中恢复时钟与本地时钟的频率补偿和相位同步,对信号的传输质量起着重要作用。基于PCIE2.0协议,采用存储器常半满的实现方式,设计一款深度、宽度均为10的弹性缓冲器。该弹性缓冲器应用于PCIE2.0的物理层设计中,并采用SMIC 55nm CMOS工艺实现。芯片测试结果表明,该弹性缓冲器满足PCIE2.0协议的要求,可正常工作于500MHz的时钟频率下,实现恢复时钟与本地时钟的频率和相位补偿,保证了接收器正常接收数据。Elastic buffer is a very important function in receiver at high-speed serial protocols such as PCI Express （ PCIE） and USB. The frequency delta and phase delta are managed perfectly to ensure data integrity by the elastic buffer when bridging local clock domain and recovered clock domain. This paper proposes elastic buffer logic in primed method to satisfy PCIE2. 0 protocol specification. The width and depth of the elastic buffer are both 10. The proposed logic is integrated into Physical Layer （ PHY ） and implemented based on 55 nm CMOS process of SMIC. The result to be measured well agreeds with the actual requirement. It can work well under the frequency of 500 MHz and ensure data to receive data correctly.

关 键 词：弹性缓冲器 频率补偿 SKP指令集 半满方式 异步FIFO 

分 类 号：TN942[电子电信—信号与信息处理]