一种用于高速D/A转换器的1.6 Gbit/s同步电路  

1.6 Gbit /s Synchronization Circuit for High Speed Digital-to-Analog Converters

作　　者：刘马良[1] 朱樟明[1] 丁昊宇 杨银堂[1] 罗泽勇[2] 

机构地区：[1]西安电子科技大学微电子学院,西安710071 [2]中国科学院长春光学机械与物理研究所,长春130033

出　　处：《北京邮电大学学报》2014年第4期69-73,共5页Journal of Beijing University of Posts and Telecommunications

基　　金：国家自然科学基金项目(61234002;61322405;61306044;61376033)

摘　　要：针对GHz采样的D/A转换器（DAC）设计及系统要求,提出了一种新型的高速同步电路.该同步电路引入高速动态比较器和触发器做低电压差分信号（LVDS）的数据接收电路,降低了功耗,实现简单;然后利用低抖动模拟延迟锁相环和数字相位检测电路选择准确的同步时钟信号,提高了同步电路工作频率范围.基于SMIC 0.18μm1.8 V CMOS工艺的仿真和测试结果显示,同步电路工作的时钟频率范围覆盖250~800 MHz,支持的数据率从500Mbit·s-1~1.6 Gbit·s-1,能用于GHz采样频率的DAC核和外部LVDS发送器接口数据的同步.A new synchronization circuit was proposed. Due to requirement of the GHz sampling D/A converter （DAC） , the circuit employs high-speed dynamic comparators and flip-flops to receive the input data from the low voltage differential signaling （LVDS） interface, which has the advantage of low power and low complexity. At the same time, this circuit adopts a low jitter analog delay locked loop and digital phase detector to obtain the proper synchronous clock, thereby, the clock frequency range of the synchro- nous circuit can be improved. Based upon the SMIC 0. 18 um 1.8 V CMOS process, the simulation gives that the clock frequency of the synchronization circuit is within the range of 250 - 800 MHz, and the data rate is 500 Mbit·s - 1 ~ 1. 6 Gbit·s -1. The circuit can be used in the synchronization of the GHz sampling DAC core and the external LVDS transmitter interface.

关 键 词：同步 低电压差分信号 D/A转换器 延迟锁相环 

分 类 号：TN402[电子电信—微电子学与固体电子学]