90nm CMOS工艺下3×V_(DD)容限静电检测电路  

3×V_(DD)-tolerant ESD detection circuit in a 90 nm CMOS process

作　　者：杨兆年[1] 刘红侠[1] 朱嘉[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2015年第1期56-61,206,共7页Journal of Xidian University

基　　金：国家自然科学基金资助项目(61376099;11235008);教育部博士点基金资助项目(20130203130002;20110203110012)

摘　　要：提出一种90nm 1.2VCMOS工艺下只用低压器件的新型3×VDD容限的静电检测电路.该电路利用纳米工艺MOSFET的栅极泄漏特性和反馈技术来控制触发晶体管并进而开启箝位器件(可控硅整流器),同时采用多级叠加结构以承受高电压应力.在静电放电时,该电路能产生38mA的触发电流.在3×VDD电压下工作时,每个器件都处于安全电压范围,在25℃时漏电流仅为52nA.仿真结果表明,该检测电路可成功用于3×VDD容限的接口缓冲器.A new low leakage 3 × VFD -tolerant electrostatic discharge （ESD） detection circuit only using the low-voltage device is proposed in a 90 nm 1.2 V CMOS process. Gate leaky characteristics of the nanoscale MOSFET and the feedback technique are used to control the trigger MOSFET and turn on the clamp device silicon-controlled rectifier （SCR）. The multi-stage stacked-transistors structure is used to sustain a high voltage stress. The proposed detection circuit can generate 38 mA current to turn on the clamp device SCR under the ESD stress. Under normal 3 × VDD operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 52 nA under the 3 × VDD bias at 25℃. Simulation result shows that the circuit can be successfully used for the 3 × VDD -tolerant I/O buffer.

关 键 词：检测电路 静电泄放 反馈 泄漏特性 叠加晶体管 

分 类 号：TN495[电子电信—微电子学与固体电子学]