EPCBC密码算法的FPGA优化实现研究  

Research on FPGA optimal implementation of EPCBC Cipher

作　　者：李浪[1,2] 邹祎[1] 贺位位[3] 李仁发[2] 

机构地区：[1]衡阳师范学院计算机系,湖南衡阳421002 [2]湖南大学信息科学与工程学院,长沙410082 [3]电子科技大学计算机科学与工程学院,成都611731

出　　处：《电子科技大学学报》2015年第1期97-100,共4页Journal of University of Electronic Science and Technology of China

基　　金：国家自然科学基金(61173036);湖南省自然科学基金(2015JJ4011);湖南省博士后基金(897203005)

摘　　要：针对资源约束的智能卡加密需要小面积实现的问题,对EPCBC加密算法从硬件上实现面积优化进行了如下研究:1)相同运算只实现一次,主程序调用32次完成加密;2)对S盒变换和密钥变换使用同一寄存器,从而节省寄存器数量;3)把密文轮操作和密钥更新放在一个模块中。通过FPGA优化结果表明,EPCBC密码算法实现面积大幅度减小,优化率达到56%,同时加密运算性能也没有降低,从而为开发受资源约束的智能卡密码硬件提供可行方案。In order to achieve small area implementation of encryption in resource-constrained smart cards, we studied the hardware optimal implementation of electronic product code block cipher（EPCBC） encryption algorithm. Firstly, each operation is accomplished only once, and the main program calls the 32 times to complete the encryption. Secondly, the same register is used in the S-box and key transformation so that the number of required registers is reduced. Thirdly, the cipher round operation and key update are put in the same module. Through field programmable gate array（FPGA） the experimental results show that the implementation area of EPCBC is greatly reduced, the optimization efficiency rate reaches 56%, and the encryption performance is not decreased so as to provide practical solutions for resource-constrained cryptographic smart cards.

关 键 词：面积优化 EPCBC加算法 FPGA VERILOG HDL 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]