基于FPGA的加密算法实现  

The Implementation of Encryption Algorithm Based on FPGA

作　　者：黄慧[1] 江荣荣 谭敏[1] 胡学友[1] 

机构地区：[1]合肥学院电子信息与电气工程系,合肥230601

出　　处：《合肥学院学报（自然科学版）》2015年第1期35-38,共4页Journal of Hefei University :Natural Sciences

基　　金：安徽省教学研究一般项目(2012jyxm4850);安徽省教育厅重点教研项目(2014jyxm313);"电子实习教学板研究与开发"企业横向项目资助

摘　　要：根据三重数据加密算法(3DES)的原理,采用全流水线和有限状态机,实现了基于现场可编程门阵列(FPGA)的3DES电路的仿真.基于Cyclone系列的EP3C40F780C6型FPGA芯片,采用自顶向下的设计思想进行电路的模块划分,有效的完成了3DES算法的总体结构和各个子模块的电路设计.利用超高速集成电路硬件描述语言(VHDL)完成了3DES加密算法的编写,并利用Altera公司的QuartusⅡ9.0综合工具对电路进行了仿真验证及逻辑综合.结果表明,该设计基本实现各模块的功能,获得了稳定的加密性能.According to the principle of the Triple Data Encryption Algorithm （3DES）, we successfully design and simulation a 3DES circuit based on Field-Programmable Gate Array （FPGA）. Based on the top-down design idea and the modularity of FPGA, we design an overall architecture of the 3DES encryption algorithm as well as the Circuit design of each sub-module, by using the EP3C40F780C6 FPGA chip of Cyclone series. We write and realize the computer programming of the 3DES encryption algorithm by employing the VHDL hardwire description language. And we perform the simulation and logic synthesis of the project using the Quartus Altera Ⅱ9.0 synthesis tool （Altera Co. Ltd. ）. Comprehensive simulation results show that the basic function of each module has been achieved and the design meets with the desired results.

关 键 词：加密算法 3DES算法 FPGA VHDL语言 全流水线 有限状态机 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]