一种高效率MCU芯片Multi-Sites测试技术  

A High Efficiency Multi-Sites Testing Technology for MCU Chip

作　　者：陈真[1,2] 陆锋[1,2] 张凯虹[2] 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2014年第11期13-15,共3页Electronics & Packaging

摘　　要：介绍了使用Multi-Sites工程测试技术提高MCU芯片测试效率的方案。针对MCU芯片Multi-Sites测试难点,阐述了在MCU芯片Multi-Sites测试中电性能测试、功能测试的影响因素和解决方案,并对MCU芯片Multi-Sites测试过程中经常遇到的干扰因素进行分析,保证MCU芯片Multi-Sites测试获得稳定可靠的性能参数,有效提高测试效率。Describes the use of multi-sites engineering testing technology to improve test MCU chip testing efficiency programs. For MCU chip multi-sites testing difficulties, elaborated factors and solutions for electrical performance testing, functional testing of the MCU chip multi-sites testing. And analyzing the interference factor MCU chip multi-sites testing process often encountered MCU chip to ensure stable and reliable test performance parameters, improve test efifciency.

关 键 词：MCU Multi-Sites 测试效率 

分 类 号：TN492[电子电信—微电子学与固体电子学]