一种SerDes的高效集成可测试性设计  

A Highly Efficient and Integrated Design for Testability of SerDes

作　　者：胡曙凡 田泽[1] 邵刚[1] 

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710068

出　　处：《计算机技术与发展》2015年第4期204-207,212,共5页Computer Technology and Development

基　　金：国家"十二五"微电子预研基金项目(51308010601;51308010711);总装预研基金(9140A08010712HK6101)

摘　　要：随着集成电路工作速度的提高以及特征尺寸的缩小,芯片设计和测试的费用越来越高。特别是进入深亚微米工艺以及超高集成度发展阶段以来,芯片的功能越来越强大,但也带来一系列设计和测试问题。测试和可测性设计的理论与技术已经成为VLSI领域中的一个重要研究方向,它们在理论和实践中都有十分突出的价值。文中基于Ser Des的测试要求,为了解决相关参数的测试难题,提出了一种针对Ser Des的可测性设计方案。回环、测试码型产生、温度检测、模拟测试总线等功能的实现,将Ser Des参数的测试难度极大降低。这种方案结构简单,效率较高,具有很好的实用价值。The expenses incurred in design and test for integrated circuit is more and more, along with the enhancement in operating speed and decreasing of the physical dimensions. Specially, when entering the deep sub-micron processing technique and ultra high integrated period, the function of IC is becoming more and more powerful, but it also brings out a series of design and testing problems. The theory and technology of testing and testable design have become an important research direction in VLSI field, and it is much more valuable in theory and practice. According to testing requirements on SerDes, for solving the problem of complex test of related parameters, a new plan of testability design is proposed. The realization of functions, such as loopback, test code generation, temperature detection and analog test bus ,reduce a great large of the test difficulty in the test of SerDes. This method has simple structure and low consumption of resources,whicn is of good value.

关 键 词：可测性设计 回环 模拟测试总线 SERDES 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]