一种用于加速度计中的五阶sigma-delta调制器  

A fifth-order sigma- delta modulator applied in accelerometer

作　　者：程磊[1] 陈中良[1] 

机构地区：[1]黄淮学院,河南驻马店463000

出　　处：《电子技术应用》2015年第3期44-47,共4页Application of Electronic Technique

摘　　要：采用C HRT 0.35μm CMOS工艺,设计实现了一种用于加速度计中的单环五阶s igma-delta(ΣΔ)调制器。在M ATLAB/Simulink下对调制器进行建模,优化参数实现一个稳定的高阶系统,利用根轨迹法分析了系统的稳定性。该电路在250 k Hz采样频率、3.3 V电压下功耗为3.4 m W。后仿真结果显示,在1k Hz信号带宽下信噪比为108.6 d B,有效位数约为18位,满足了加速度计对后级高精度调制器的要求。A single-loop fifth-order sigma-delta（∑△） modulator circuit applied in accelerometer is designed using CHRT 0. 35 μm CMOS process. The modulator is modeled and analyzed in MATLAB/Simulink and parameters are optimized to achieve a stable high-order system. The system stability is analyzed based on the root locus. The power dissipation of the circuit is about 3.4 mW with sampling frequency 250 kHz at a 3.3 V power supply. The post-simulation result indicates that the signal-to-noise -ratio （SNR） is 108.6 dB with 18-bit resolution over a signal bandwidth of 1 kHz, which meets the accelerometer＇s demand for subsequent stage high-precision modulator.

关 键 词：低通∑△调制器 建模 高阶 根轨迹 

分 类 号：TN79[电子电信—电路与系统]