DDR3 PHY的DFT集成设计和验证  

Design and Verification of DFT Integration for DDR3 PHY

作　　者：袁秋香[1] 方粮[1] 

机构地区：[1]国防科技大学计算机学院并行与分布重点实验室,长沙410073

出　　处：《高性能计算技术》2012年第5期30-35,共6页

基　　金：本文获国家“863”高技术研究与发展计划基金项目（2011BAH04B05）的资助.

摘　　要：目前，为了加快芯片的上市周期，SoC（System on Chip）更趋向于使用可复用的IP（Intellectual Property）核。由于高速内存接口DDR3采用了8次预取技术，其主流速度可以达到800Mbps，因而也备受青睐。当DDR3PHY作为一个高速IP核时，其DFT（Design For Testability）集成设计和验证难度加大。本文采用了从JTAG（Joint Test Action Group）接口中加栽测试码，进而启动内部的BIST（Built-In Self Test）逻辑来控制内外部loopback路径的方法来验证DDR3 PHY的数据传输功能。这为验证高速接口IP核的模拟和数字路径的高传输速率提供了有效的方法，还能有效地降低测试成本。此外，对DDR3 PHY进行综合后的物理设计时，由于布局布线难度较大，使得DDR3 PHY的工作频率会降低。针对这种情况，在验证时采用降低JTAG的测试时钟频率的方法，再去采样DDR3 PHY的数据，得到的测试码仍能使其在测试时正常工作。At present, in order to shorten the design cycle, reusing IP（Intellectual Property） core is the trend of SoC（System on Chip）. Due to the eight prefetching technology in a cycle, the mainstream speed of high-speed memory interface DDR3 can reach 800 Mbps, which is also very popular. It is difficult to design and verify DFT（Design for Testability） integration for DDR3 PHY as a high-speed IP core. This paper verifies the data transmission function of DDR3 PHY by such a method that loading test code into JTAG （Joint Test Action Group） interface to start internal BIST（Built-In Self Test） logic to control the internal and external loopback path, which provides an effective method to verify the analog and digital path of high transmission rate for high-speed interface IP core and can effectively reduce the test cost. In addition, because it is hard to do physical design, which makes the working frequency of synthesizable DDR3 PHY reduce. In such a circumstance, by reducing test clock frequency of JTAG to sample the data of DDR3 PHY, the test code can still make it work normally during the test.

关 键 词：DDR3 PHY DFT集成设计和验证 LOOPBACK JTAG降频采样 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]