基于扫描线填充的三角形图元双向光栅化技术  

New Triangle Primitive Rasterization Technique Based on Bi-direction Scan-line Filling

作　　者：田泽[1] 刘天江[1] 张骏[1] 许宏杰[1] 黎小玉[1] 

机构地区：[1]中国航空工业西安航空计算技术研究所,西安710068

出　　处：《小型微型计算机系统》2015年第6期1398-1402,共5页Journal of Chinese Computer Systems

摘　　要：光栅化是图形处理器3D引擎流水线的关键阶段,实现了从连续方式描述的图形到离散的像素点间的转换,如何提高光栅化效率是图形处理器设计的关键技术之一.本文分析了基于Bresenham算法的线填充算法,提出一种基于扫描线填充算法的三角形图元双向光栅化技术,称为BSF,实现了同时从两个方向对三角形图元进行光栅化,将三角形光栅化效率提升约39.02%,代价是增加了光栅化单元的规模和复杂度.基于BSF设计了光栅化单元,并采用Xilinx的ISE工具进行综合,在Xilinx Vertex6 XC6VLX760 FPGA上进行原型验证,电路工作频率可以达到202M Hz,测试结果表明可以正确快速的实现光栅化功能.在SMIC 65nm CMOS工艺下,采用Synopsys Design-Compiler对光栅化单元进行综合,电路工作频率达到330MHz,满足设计需求.Rasterization is a key phase of 3D engine pipleline in GPU, which implements the conversion of continuous described graph- ics to a series of discrete pixels. How to increase the efficiency of rasterization is one of the most important techniques of GPU design. This paperanlyzes the line filling algorithm based on the bresenhamalgnrithm, and proposes a new rasterization technique based on bi- direction scan-line filling,called BSF, which implements triangle primitive rasterizationfrom two directions in the same time, and up- grades the rasterizationefficiency by 39.02%. The price of new technique is scale and complication increasing. Further, we design ras- terization unit（ RU ） in GPU based on BSF, and use the Xilinx ISE toolsto implement the RU on Xilinx Vertex6 XC6VLX760 FI^A for prototype verification. As a result,the frequency of prototype is up to 202MHz and RUfunctionsare correct. In addition,we synthe- size the RU RTL under SMIC 65nm CMOS library by using Synopsys Design-Compiler. the frequency ofRU ASIC design is up to 330MHz, which meets the design requirements.

关 键 词：图形处理器 光栅化 扫描线 BRESENHAM 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]