一种高速数模混合倒装芯片协同仿真技术研究  

Research on a High Speed Transceiver Co-simulation Technology with Flip-chip Package

作　　者：蔡叶芳[1] 田泽[1] 邵刚[1] 唐龙飞[1] 刘宁宁[1] 

机构地区：[1]西安航空计算技术研究所,陕西西安710068

出　　处：《计算机技术与发展》2015年第6期56-59,共4页Computer Technology and Development

基　　金："十二五"微电子预研(51308010601;51308010711);总装预研基金(9140A08010712HK6101)

摘　　要：串行数据率的不断提高使得传输信号的波长和板中传输线长度可比拟,分布参数显现出不可忽视的影响。文中提出了一种全信道仿真的方法,在HFSS软件中对倒装焊管壳进行建模,在Si Wave软件中对PCB链路进行分析,并分别提取出S参数和Spice网表,以及高速数模混合So C芯片中Ser Des接口中Tx及Rx模块版图寄生参数提取后的RCX网表。在Cadence Spectre软件下进行协同仿真的方法,较好地预计出了高速数模混合倒装焊芯片在版图、封装、管壳以及信道影响情况下的传输特性,为电路设计以及改进提供了依据。The paracitic effect has played a more important role when the waveform length has compared to the channel length in terms of increasing baudrate of serial communication. In this paper,a full channel simulation method has been proposed. The flip-chip package model has been extracted using HFSS,the PCB channel has been analyzed in SiWave as while,both S parameter and Spice model has been extracted and simulated with Rx and Tx RCX netlist using Spectre simulator. The simulation has accurately predicted the perform-ance of high speed circuit with parasitic effect of layout,package,channel,and the method is an effective way for circuit optimization.

关 键 词：SERDES 封装 管壳 信道 协同仿真 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]