一种高速SERDES抖动容限的高效仿真验证方法  

A Highly Efficient Simulation Verification Method for High Speed SERDES Jitter Tolerance

作　　者：邵刚[1] 田泽[1] 李世杰[1] 吕俊盛[1] 

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710065

出　　处：《计算机技术与发展》2015年第7期217-220,共4页Computer Technology and Development

基　　金："十二五"微电子预研(51308010601;51308010711);总装预研基金(9140A08010712HK6101)

摘　　要：文中针对高速SERDES总线接收端的验证提出了一种抖动容限验证方法,有效降低了流片风险。由于受温度、布线、信道寄生的影响较大,高速SERDES需要保证在恶劣信道,尤其是大的抖动干扰时仍能稳定工作,设计阶段对接收电路抗抖动特性的评估是一个复杂的验证过程,鲜有报道。文中基于对PCIE,SRIO,FC等信道和协议的研究,提出一种快速高效的RX端抖动容限的验证评估方法。经验证采用该模型能方便准确地评估RX的特性,经电路流片后,实际测试表明,采用该方法评估的抖动容限结果与测试结果精确符合,可在设计阶段显著优化RX的性能,并大幅降低流片的风险。Aiming at high speed SERDES bus validation at the receiving end, put forward a jitter tolerance verification method, effectively reducing the risk of a flow chip. For many factor can affect SERDES, such as temperature, wiring and the parasitic of channel,it needs to work stably in many cases, the assessment of jitter characteristics for the receiving circuit in design phase is a complex validation process, with few reports. Based on the protocol of PCIE, SRIO and FC, a fast and efficient verification and evaluation method is proposed for RX end jitter tolerance. The model proposed in this method can accurately assess the convenient characteristics of RX. The test result indicates that the jitter tolerance evaluated by the model can tally with the test results accurately ,significantly optimizing the performance of RX in design stage and reducing the risk of flow chip largely.

关 键 词：SERDES 抖动容限 验证 CDR 时钟恢复电路 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]