高速串行接口接收端阻抗校正电路设计  

An Impedance Calibration Circuit Design of High-speed Serial Interface Receiver

作　　者：虞鑫栋 姚穆[1] 陈玉虎[1] 李优[1] 赵建中[1] 张锋[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2015年第12期54-58,共5页Microelectronics & Computer

基　　金：国家高技术研究发展计划("八六三"计划)项目(2011AA010403);国家科技重大专项项目(2014ZX02302002)

摘　　要：研究并设计了一款应用于高速串行接口接收端的阻抗自校正电路,用以降低因接收器输入端阻抗不匹配而造成的信号反射,提高信号完整性.阻抗自校正电路采用由比较器和阻抗校正单元组成的数模混合负反馈环路结构,其中阻抗校正单元由有限状态机和接收端电阻阵列的复制单元构成,且电阻阵列由46个相同的电阻单元和一个半权重电阻单元并联组成.仿真验证显示,阻抗自校正电路实现了3%的校正精度,±35%的校正范围,回波损耗(S11)在12.5GHz时小于-15dB.该电路在55nm CMOS工艺设计,面积为218μm×133μm,功耗为7.43mW.An impedance self-calibration circuit applying to high-speed serial interface receiver was studied and designed.It is used to reduce the signal reflection because of impedance mismatch of the receiver input channel and improve the signal integrity.Impedance self-calibration circuit using digital-analog hybrid negative feedback loop structure which is composed of comparator and impedance calibration unit.The impedance calibration unit is made up of finite-state machine and replication cell of the receiver resistor array,and the resistor array consist of 46 same resistor unit and one half-weight resistor unit with parallel hybrid.Simulation and verification indicates that the calibration precision of the impedance self-calibration circuit can reach to 3% and calibration range can reach to±35%,when the frequency is 12.5 GHz the return loss is less than-15 dB.The chip was taped out in 55 nm CMOS technology,it occupied 218μm×133μm and the power consumption is 7.43 mW.

关 键 词：高速串行接口 阻抗自校正 数模混合 校正精度 回波损耗 

分 类 号：TN402[电子电信—微电子学与固体电子学]