基于AXI总线高效能DDR3控制器IP软核的硬件实现  

Hardware Implementation of a High Performance DDR3 Controller based on AXI Bus Interface

作　　者：陈宏铭 钟昌瑾 

机构地区：[1]智原科技,上海200233

出　　处：《中国集成电路》2015年第12期38-42,64,共6页China lntegrated Circuit

摘　　要：DDR3 SDRAM是新一代的内存技术标准,也是目前内存市场上的主流。大量的嵌入式系统或手持设备也纷纷采用DDR3内存来提高性能与降低成本,随着越来越多的So C系统芯片中集成DDR3接口模块,设计一款匹配DDR3的内存控制器IP软核具有良好的应用前景。本文在研究了DDR3的JEDEC标准的基础上,设计出DDR3控制器IP软核的整体架构,并使用Verilog HDL语言完成DDR3控制器IP软核。在分析了40nm DDR3 PHY测试芯片的基本性能的基础上,设计DDR3控制器IP软核的接口模块。搭建利用AXI总线对DDR3控制器IP软核发出直接激励的仿真验证平台,针对设计的具体功能进行仿真验证,并在Xilinx XC5VLX330T-FF1738-2开发板上实现对DDR3存储芯片基本读/写操作控制。在EDA仿真环境下,DDR3控制器IP软核的总线利用率达到66.6%。DDR3 SDRAM is a new generation of memory standard and the dominant mainstream system memory product in the DRAM market today. A large number of embedded systems including portable devices are using DDR3 memory devices to have good performance and reduce the system cost. More and more SoCs had been integrated with DDR3 interface module, so design a DDR3 SDRAM controller having on DDR3 standard JEDEC specification, we develops the overall architecture of a good application prospects. Based DDR3 controller. The DDR3 controller is designed by Verilog HDL language. An interface between the DDR3 controller and a 40nm PHY testchip is designed based on the analysis the performance of the PHY chip. A DDR3 SDRAM controller simulation and verification platform had been proposed and the designed modules are simulated. The FPGA shows the basic read/write operations are implemented to DDR3 SDRAM on Xilinx XC5VLX330T-FF1738-2 evaluation board. Under the EDA simulation environment, bus utilization of the proposed DDR3 controller can reach 66.6%.

关 键 词：DDR3内存 AXI总线 JEDEC标准 XILINX FPGA 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]