硅基深宽比结构与SiO2薄膜的干法刻蚀方法研究  

Dry Etching Technique Study During Etching of High-aspect-ratio Silicon Structure and SiO_2 Film

作　　者：颜改革 韩敬宁[1] 殷志富[1] 邹赫麟[1] 

机构地区：[1]大连理工大学机械工程学院,辽宁省微纳米技术及系统重点实验室,辽宁大连116023

出　　处：《仪表技术与传感器》2015年第11期1-3,14,共4页Instrument Technique and Sensor

摘　　要：文中研究了贯穿刻蚀硅基直壁沟槽及沟槽底部SiO_2薄膜过刻蚀的深反应离子刻蚀(DRIE)工艺过程。首先,研究了DRIE刻蚀钝化时间比(T_(SF6)∶T_(C4F8))对硅刻蚀形貌的影响。通过工艺参数优化,采用刻蚀钝化时间比分别为9 s/2 s、11 s/2 s(C_4F_8)下电极射频功率为40 W)和11 s/2 s(C_4F_8下电极射频功率为0 W)的三步刻蚀工艺,贯穿刻蚀了宽度为150μm,深度为300μm的直壁沟槽。其次,研究了C_4F_8(八氟环丁烷)钝化气体对SiO_2薄膜过刻蚀的现象,采用降低C4F8下电极射频功率方法,减小了C4F8对SiO_2薄膜过刻蚀。In this paper, the silicon etching process during etching of vertical wall groove by deep reactive ion etching （ DRIE） technique was studied .Firstly, the influence of the ratio of the etching and passivation time （ TSF6：TC4F8 ） on the profile of the etched silicon hole was investigated .By optimizing the process parameters , three etching steps with the ratio of the etching/pas-sivation time of 9 s/2 s, 11 s/2 s（ C4 F8 power was set at 40 W） and 11s /2s （ C4 F8 power was set at 0 W） were usedW.ith the op -timized three etching steps , the groove with width of 150μm and depth of 300μm can be fabricated with vertical side wall .Second-ly, the effect of the passive gas （C4 F8） power on the degree of SiO2 over etching was studied.By decreasing the C4F8 power, the degree of SiO 2 over etching can be mitigated .

关 键 词：深反应离子刻蚀 刻蚀钝化时间比 射频功率 黑硅 SIO2薄膜 

分 类 号：TN405[电子电信—微电子学与固体电子学]