基于Verilog HDL的IIC总线IP核设计  

The Design of IIC Bus IP Core Based on Verilog HDL

作　　者：朱诚诚[1] 石晶晶[1] 陈斯[1] 张萌[2] 

机构地区：[1]东南大学电子科学与工程学院,南京211189 [2]东南大学国家ASIC中心,南京210096

出　　处：《电子器件》2015年第6期1336-1340,共5页Chinese Journal of Electron Devices

摘　　要：设计片上系统时往往需要各种数据接口,为了解决片上系统间的数据传输的实际需求,设计了一种更为简捷的IIC总线接口,并利用Verilog HDL语言进行了IIC总线IP核的设计,使得所设计的IIC总线接口具有良好的移植性,实现了不同速率模式下的数据传输,可以方便地应用到片上系统、各类集成电路数据接口等设计中。When doing system on a chip,various data interfaces are often needed. In order to solve the data trans-mission between the systems on chip,the design of a more brief IIC bus interface is completed using Verilog HDLlanguage to realize the design of IIC bus IP core,Thus,the IIC bus interface design has good portability and realizesdifferent rates of data transmission,which also can be applied to systems on chip design easily.

关 键 词：专用集成电路 IIC总线IP核设计 仿真及硬件测试 VERILOG HDL 状态机 

分 类 号：TP492[自动化与计算机技术]