填充辅助多晶硅图形的参数成品率版图优化  

Layout optimization of parametric yield by filling dummy polysilicon pattern

作　　者：韩晓霞[1] 韩雁[1] 

机构地区：[1]浙江大学微电子与光电子研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2015年第12期2333-2339,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家青年自然科学基金资助项目(61106035);国家自然科学基金资助项目(61274035)

摘　　要：在纳米工艺下,为了更好地抵抗工艺波动的影响,减小位于标准单元边界处的MOS管沟道长度随聚焦误差引起的变化,提出在现有版图基础上在两相邻标准单元间填充最优辅助多晶硅图形的版图优化方式以提高芯片的参数成品率.通过修改所填充的辅助多晶硅图形的线宽、线间距以及线条数的特征属性,利用光刻仿真得到针对不同多晶硅特征图形的最优辅助多晶硅图形,由此构建一个查表模型.在现有版图基础上,对位于标准单元边界处的各个MOS管提取出其相应的多晶硅特征图形,并利用所提取出的特征图形查找查表模型分别得到最优的辅助多晶硅图形,根据版图设计规则将辅助多晶硅图形填充至两相邻标准单元之间.分别对测试版图优化前后进行光刻仿真分析,结果表明:采用所提出的版图优化方法在不影响位于标准单元内的MOS管的多晶硅线宽变化前提下,位于标准单元边界的MOS管的多晶硅线宽变化量从版图优化前的10.58nm降低至4.79nm.A layout optimization design method by filling dummy polysilicon pattern between two adjacent standard cells for existing layout was proposed to improve the parametric yield to resist the effect of process variation and reduce the linewidth variation of the MOS transistors located at the boundary of standard cells due to defocus under the nano technology. Through the modification of the feature attribute of the dummy polysilicon pattern, such as linewidth, line-to-line space and the number of lines, the optimal dummy polysilicon pattern for the different feature patterns of gate poly could be obtained by using lithography simulation. A lookup table model for optimal dummy polysilicon was created. On the basis of the existing layout, the feature pattern of gate poly for the MOS transistors located at the boundary of standard cells was extracted. According to the extracted feature pattern, the optimal dummy polysilicon pattern searched from the lookup table was inserted between two adjacent standard cells following the design rules. The lithography simulation was taken for a test layout before and after optimization. Results show that the linewidth variation of gate poly for MOS transistors located in the standard cells is not affected when use the proposed layout optimization method, and the linewidth variation of gate poly for MOS transistors located at the boundary of standard cells is reduced from 10.58 nm to 4.79 nm.

关 键 词：参数成品率 聚焦误差 光刻仿真 版图优化 工艺波动 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN492