基于多核的嵌入式HEVC解码器并行优化  

Parallel Optimization of Multi-core Embedded HEVC Decoder

作　　者：刘鹏[1] 杨斌[1] 张翠芳[1] 

机构地区：[1]西南交通大学信息科学与技术学院,成都610031

出　　处：《单片机与嵌入式系统应用》2016年第7期23-26,30,共5页Microcontrollers & Embedded Systems

摘　　要：基于一款ARM big.LITTLE架构8核嵌入式处理器,设计了一种波前并行解码优化方法,主要包括像素重构并行、去方块滤波并行、样点自适应补偿并行等内容,突破了模块设计的边界限制,改善了Cache命中率,提升了解码效率。在Exynos5Octa处理器平台上的运行测试达到了较好的解码效果。In this paper, an approach of Wavefront Parallel Processing （WPP） is proposed using eight cores processor based on ARM big LITTLE architectures. The approach includes the pixel reconstruction, parallel to the filter, parallel to the sample point adaptive compen sation and other contents. The approach breaks through the boundary limit of module design, improves the hit rate of Cache, and im proves the decoding efficiency. The overall solution achieves satisfactory result by running in Exynos50cta platform.

关 键 词：HEVC 解码器 多核并行计算 Exynos5 Octa 

分 类 号：TN764[电子电信—电路与系统] TN919.81