动态随机存储器器件研究进展  

Research progresses of dynamic random access memory devices

作　　者：吴俊[1] 姚尧[1] 卢细裙 王鹏飞[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《中国科学：物理学、力学、天文学》2016年第10期36-45,共10页Scientia Sinica Physica,Mechanica & Astronomica

基　　金：国家自然科学基金资助项目(编号:61322404)

摘　　要：动态随机存储器芯片是集成电路中销售量和销售额最大的单一产品.本文介绍了DRAM存储单元的基本原理并回顾了DRAM的技术发展与关键创新,总结了多种先进技术节点的DRAM芯片制造的关键工艺技术.分析了电容结构、阵列访问晶体管、存储器单元结构等方面的技术演进.介绍了多种基于U形沟道晶体管的DRAM存储单元以及6F2存储单元的制造方法.基于多项关键技术突破,对下一代DRAM芯片的关键器件工艺的技术发展趋势进行了推测.即:(1)阵列选择晶体管持续使用U形晶体管;(2)低k材料会被大规模使用来降低位线寄生电容;(3)提高灵敏放大电路的灵敏度和随温度来动态调整刷新频率来降低对存储电容的要求;(4)更多关注低功耗设计而不是一味地增大存储容量.In this paper, the dynamic random access memory（DRAM） cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F2 memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F2 DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that（1） U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm;（2） low k material will be required for decreasing the bitline parasitic capacitance;（3） sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance;（4） low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.

关 键 词：动态随机存储器 短沟道效应 掩埋字线 阵列访问晶体管 存储电容 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]