三维功率MOSFET器件漏极持续电流分析方法  

Analysis method of drain sustained current of 3D power MOSFET

作　　者：林洁馨[1] 杨发顺[1] 马奎[1] 唐昭焕[1] 傅兴华[1] 

机构地区：[1]贵州大学大数据与信息工程学院,贵州贵阳550025

出　　处：《现代电子技术》2016年第24期137-140,共4页Modern Electronics Technique

基　　金：国家自然科学基金地区科学基金项目(61464002);贵州省科技合作项目(黔科合LH字[2015]7636);贵州省科学技术基金(黔科合J字[2014]2066号)

摘　　要：二维功率MOSFET器件的漏极持续电流是一个受限于封装形式和芯片设计的极限参数,传统分析方法是通过器件的最大耗散功率对其进行评估。基于三维集成技术的功率MOSFET器件,散热路径热阻难于精确确定,故提出一种针对三维集成功率MOSFET器件,以晶格自加热效应为基础的漏极持续电流分析方法,并以一颗开关工作状态下的100 V功率VDMOS器件为研究对象,在正向设计阶段分析了功率VDMOS器件漏极持续电流的导通偏置条件。最后通过流片结果验证了该方法的可行性。The drain sustained current of 2D power MOSFET is an absolute parameter limited by encapsulation mode and chip design, and is evaluated by the traditional analysis method via the maximum dissipation power of devices. It is difficult to determine the accurate thermal dissipation resistance of the power MOSFET based on 3D integration technology, so a drain sus- tained current analysis method based on the lattice self-heating effect is proposed for the 3D integration power MOSFET. A 100 V power VDMOS working at switching state is taken as the research object to analyze the breakover bias conditions of the drain sustained current of the power VDMOS in forward design phase. The feasibility of the method was verified by stream chip results.

关 键 词：漏极持续电流 三维集成 自加热效应 导通偏置条件 

分 类 号：TN701-4[电子电信—电路与系统]