一种解决半选择单元干扰问题的SRAM设计方案  

A SRAM Design Solution to Half-Select Disturbance Problem

作　　者：程瑞娇 薛晓勇[1] 林殷茵[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2016年第6期783-789,共7页Journal of Fudan University：Natural Science

摘　　要：半选择单元的干扰问题是SRAM工作电压无法随工艺微缩持续降低的主要原因,同时,作为常用写稳定性帮助策略和提高读写速度的策略,PWB中字线增强时间点对半选择单元干扰问题的影响非常值得关注.本文深入分析了半选择单元干扰问题的电路机理和PWB稳定性策略,提出了一种基于交叉耦合PMOS管的HFPWB创新方案,在避免了半选择单元干扰问题的同时,给出了字线增强的具体时间点.仿真结果表明本文提出的电路结构可以同时提高全选单元和半选择单元的稳定性,并可以提高读速度达17.1%.Half-selected disturbance is an inevitable problem in 6T Static Random Access Memory.Partial WL boost is a usual write stability assist and speed improve strategy,which＇s boost timing is critical to half-selected cell.To solve these problems,this paper analyzes the half-selected disturbance issues and partial WL boost circuit mechanism,and an innovative Half-Select free partial WL boost（HFPWB）solution is proposed.HFPWB strategy based on cross-coupled PMOS,it will stable the half-selected cell＇s state and give the boost timing at the same time of cross-coupled PMOS begin to work.The simulation results show the circuit presented in this paper can improve the stability of the selected cells and the half-selected cells,and reading speed up to 17.1%.

关 键 词：静态随机存储器 半选择单元 干扰 字线增强 写稳定性 

分 类 号：TN402[电子电信—微电子学与固体电子学]