一种基于FPGA进位链的时间数字转换器  

A TDC Based on Carry-in Lines of the FPGA

作　　者：王巍[1] 周浩[1] 熊拼搏 李双巧 杨皓[1] 杨正琳[1] 袁军[1] WANG Wei ZHOU Hao XIONG Pinbo LI Shuangqiao YANG Hao YANG Zhenglin YUAN Jun(College of Electronics Engineering~International Semiconductor College, Chongqing University of Posts and Telecommunications, Chongqing 400065, P. R. China)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《微电子学》2016年第6期777-780,787,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404019)

摘　　要：提出了一种基于Xilinx Virtex-5FPGA的时间数字转换器。利用Virtex-5中专用进位链CARRY4构造的延迟链,对时钟周期进行内插以得到更高精度的测量。此外,运用布局布线约束来减少延迟链的不一致性,降低了微分非线性（DNL）以及积分非线性（INL）。仿真结果表明,最低有效位（LSB）为52.22ps,精度（RMS）约为25ps,INL为0~0.9LSB,DNL为-0.03~0.1LSB。The design and implementation of a high resolution time-to-digital converter in a field programmable gate array was proposed.Dedicated carry-in lines in CARRY4 block of the Virtex-5FPGA were utilized for time interpolation,which had realized the fine time measurement within a system clock period.Meanwhile,place and route（PAR）constraints were applied to eliminate the asymmetry of the delay chain,which had resulted in very small integral nonlinearity（INL）and differential nonlinearity（DNL）.The simulation results showed that the RMS time resolution of TDC was about 25 ps,the LSB was 52.22 ps.The INL was 0-0.9LSB,and the DNL was-0.03-0.1LSB.

关 键 词：时间数字转换器 进位链 CARRY4 布局布线 可编程逻辑器件 

分 类 号：TN722.3[电子电信—电路与系统]