一种基于0.18μm CMOS工艺的高响应度APD  

High responsivity APD based on 0.18 μm CMOS technology

作　　者：王巍[1] 陈丽[1] 鲍孝圆 陈婷[1] 徐媛媛[1] 王冠宇[1] 唐政维[1] WANG Wei CHEN Li BAO Xiao-yuan CHEN Ting XU Yuan-yuan WANG Guan-yu TANG Zheng-wei(College of Electronics Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, Chin)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《激光与红外》2017年第1期62-66,共5页Laser & Infrared

摘　　要：设计了一种基于0.18μm CMOS工艺的高响应度雪崩光电二极管(APD)。该APD采用标准0.18μm CMOS工艺,设计了两个P+/N阱型pn节,形成两个雪崩区以产生雪崩倍增电流。雪崩区两侧使用STI(浅沟道隔离)结构形成保护环,有效地抑制了APD的边缘击穿;并且新增加一个深N阱结构,使载流子在扩散到衬底之前被大量吸收,屏蔽了衬底吸收载流子产生的噪声,用以提高器件的响应度。通过理论分析,确定本文所设计的CMOS-APD器件光窗口面积为10μm×10μm,并得到了器件其他的结构和工艺参数。仿真结果表明:APD工作在480 nm波长的光照时,量子效率达到最高90%以上。在加反向偏压-15 V时,雪崩增益为72,此时响应度可达到2.96 A/W,3 d B带宽为4.8 GHz。A high responsivity APD based on 0. 18 μm complementary metal-oxide-semiconductor （CMOS） process is designed. With the standard 0. 18 μm CMOS technology, two P ＋/N-well type pn junctions are designed to form two avalanche regions in order to produce avalanche multiplication current, and the guard-ring structure is formed with STI （Shallow Trench Isolation） structure on both sides of the avalanche region,which restrains the edge-breakdown effectively. A deep N-well structure has been applied in the APD to absorb a large number of carriers before they spread to the substrate, which screened the excessed noise and improved the responsivity of the device. Though theoretical analysis,the optical window area is 10μm × 10 μm,other structure and process parameters of the CMOS-APD are also confirmed. The simulation resuhs show that at wavelength of 480 nm, the quantum efficiency reaches up to 90%. The avalanche gain is about 72, the responsivity is 2. 96 A/W and 3 dB bandwidth is about 4. 8 GHz when the bias voltage is - 15 V.

关 键 词：CMOS-APD 雪崩增益 响应度 带宽 

分 类 号：TN364.2[电子电信—物理电子学]